1. Field of the Invention
The present invention relates to signal integrity (SI) analysis performed in conjunction with static timing analysis of a hierarchical design, and particularly to using interface logic models (ILMs) in this SI analysis.
2. Description of the Related Art
Static timing analysis of complex circuits is a computationally expensive operation. Static timing analysis (STA) refers to a method of validating the timing performance of a design by checking all possible paths for timing violations. Unfortunately, when routing is performed for circuits in the design, the proximity of two nets could result in undesirable crosstalk in which a signal on one net could affect the timing of a signal on the other net.
An operation called signal integrity (SI) analysis can be performed in conjunction with STA to evaluate the dynamic effects of cross-coupling between proximate nets. Typically, SI analysis is addressed using physical synthesis (e.g. sizing of drivers, inserting buffers, optimizing placement of components, and isolating nets) and routing. Unfortunately, performing this SI analysis adds significant complexity to STA. Thus, accomplishing SI analysis on a full chip may be practically impossible. Moreover, even if SI analysis is possible, it takes an inordinate amount of time. For example, for complex designs, such as system-on-a-chip (SOC) designs, SI analysis could take many hours or even days to run.
Therefore, a need arises for a method of performing SI analysis that provides accurate and time efficient results.